Random access memory (RAM) provides fast, cost-effective, volatile storage for computing devices. The Joint Electron Device Engineering Council (JEDEC) provides memory standards for storage devices. One such standard currently in use is the DDR4 SDRAM (double data rate fourth generation synchronous dynamic random-access memory) standard, which provides higher module density, lower voltage specifications, and higher data rate transfer speeds than previous standards (i.e., DDR, DDR2, and DDR3). Dynamic random access rams (DRAMs) are available with different data widths. Four bits wide DRAMs and eight bits wide DRAMs are generally identified as x4 DRAM and x8 DRAM, respectively.
Conventional techniques to support both x8 DRAMs and x4 DRAMs in the same memory controller or data buffer typically have the disadvantage of requiring multiplexing logic in the data strobe (DQS) path. When a controller or data buffer circuit is designed with matching DQ-DQS receivers, the delay penalty in the DQS path also applies to the data (DQ) paths, which hurts latency performance of the device.
It would be desirable to implement support for multiple widths of dynamic random access memories (DRAMs) in DDR controllers and/or data buffers without incurring a penalty of additional multiplexing logic.